Known CVE vulnerabilities and GitHub Security Advisories affecting the SUSE:Linux Enterprise Micro 5.3 package ucode-intel, with affected version ranges, CVSS severity, EPSS exploit prediction, and CISA KEV status.
CVEs (47)
CVE-2024-23918 — CVSS 8.8 (high): Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX may allow a…
CVE-2023-23583 — CVSS 8.8 (high): Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may allow an authenticated user to potentially…
CVE-2023-45745 — CVSS 7.9 (high): Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially…
CVE-2025-22889 — CVSS 7.9 (high): Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged…
CVE-2023-49141 — CVSS 7.8 (high): Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of…
CVE-2023-42667 — CVSS 7.8 (high): Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable…
CVE-2025-20109 — CVSS 7.8 (high): Improper Isolation or Compartmentalization in the stream cache mechanism for some Intel(R) Processors may allow an authenticated user to…
CVE-2022-21216 — CVSS 7.5 (high): Insufficient granularity of access control in out-of-band management in some Intel(R) Atom and Intel Xeon Scalable Processors may allow a…
CVE-2025-22839 — CVSS 7.5 (high): Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable processors may allow a privileged user to…
CVE-2025-22840 — CVSS 7.4 (high): Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated…
CVE-2025-32086 — CVSS 7.2 (high): Improperly implemented security check for standard in the DDRIO configuration for some Intel(R) Xeon(R) 6 Processors when using Intel(R)…
CVE-2022-33196 — CVSS 7.2 (high): Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R) Processors when using Intel(R) Software…
CVE-2022-41804 — CVSS 7.2 (high): Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some Intel(R) Xeon(R) Processors may allow a privileged user to…
CVE-2024-21820 — CVSS 7.2 (high): Incorrect default permissions in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX may allow a…
CVE-2024-24853 — CVSS 7.2 (high): Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a…
CVE-2025-20053 — CVSS 7.2 (high): Improper buffer restrictions for some Intel(R) Xeon(R) Processor firmware with SGX enabled may allow a privileged user to potentially…
CVE-2025-26403 — CVSS 7.2 (high): Out-of-bounds write in the memory subsystem for some Intel(R) Xeon(R) 6 processors when using Intel(R) SGX or Intel(R) TDX may allow a…
CVE-2024-39355 — CVSS 6.5 (medium): Improper handling of physical or environmental conditions in some Intel(R) Processors may allow an authenticated user to enable denial of…
CVE-2025-20054 — CVSS 6.5 (medium): Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially enable…
CVE-2023-28746 — CVSS 6.5 (medium): Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R)…
CVE-2022-40982 — CVSS 6.5 (medium): Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R)…
CVE-2023-39368 — CVSS 6.5 (medium): Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to potentially enable…
CVE-2024-36293 — CVSS 6.5 (medium): Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with Intel(R) SGX may allow an authenticated user…
CVE-2025-20103 — CVSS 6.5 (medium): Insufficient resource pool in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially…
CVE-2024-24980 — CVSS 6.1 (medium): Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially…
CVE-2023-22655 — CVSS 6.1 (medium): Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a…
CVE-2022-33972 — CVSS 6.1 (medium): Incorrect calculation in microcode keying mechanism for some 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged…
CVE-2023-23908 — CVSS 6.0 (medium): Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a privileged user to potentially enable…
CVE-2024-25939 — CVSS 6.0 (medium): Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially…
CVE-2023-47855 — CVSS 6.0 (medium): Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially…
CVE-2022-38090 — CVSS 6.0 (medium): Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may allow a privileged…
CVE-2024-43420 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel…
CVE-2025-24495 — CVSS 5.6 (medium): Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow an authenticated…
CVE-2024-28956 — CVSS 5.6 (medium): Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow…
CVE-2024-45332 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect…
CVE-2025-20623 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R)…
CVE-2023-38575 — CVSS 5.5 (medium): Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to…
CVE-2024-23984 — CVSS 5.3 (medium): Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user to potentially enable information…
CVE-2024-31068 — CVSS 5.3 (medium): Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow privileged user to potentially enable denial…
CVE-2023-43490 — CVSS 5.3 (medium): Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow a privileged user to…
CVE-2024-24968 — CVSS 5.3 (medium): Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an privileged user to potentially enable a…
CVE-2025-20012 — CVSS 4.9 (medium): Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated user to potentially enable information…
CVE-2024-21853 — CVSS 4.7 (medium): Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors may allow an…
CVE-2023-46103 — CVSS 4.7 (medium): Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an authenticated user to…
CVE-2025-31648 — CVSS 3.9 (low): Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and…
CVE-2024-37020 — CVSS 3.8 (low): Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Processors may allow an…
CVE-2023-45733 — CVSS 2.8 (low): Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enable partial…