ucode-intel (SUSE:Linux Enterprise Module for Basesystem 15 SP7) — known CVEs & security advisories

Known CVE vulnerabilities and GitHub Security Advisories affecting the SUSE:Linux Enterprise Module for Basesystem 15 SP7 package ucode-intel, with affected version ranges, CVSS severity, EPSS exploit prediction, and CISA KEV status.

CVEs (17)

• CVE-2025-22889 — CVSS 7.9 (high): Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged…
• CVE-2025-20109 — CVSS 7.8 (high): Improper Isolation or Compartmentalization in the stream cache mechanism for some Intel(R) Processors may allow an authenticated user to…
• CVE-2025-22839 — CVSS 7.5 (high): Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable processors may allow a privileged user to…
• CVE-2025-22840 — CVSS 7.4 (high): Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated…
• CVE-2025-32086 — CVSS 7.2 (high): Improperly implemented security check for standard in the DDRIO configuration for some Intel(R) Xeon(R) 6 Processors when using Intel(R)…
• CVE-2025-20053 — CVSS 7.2 (high): Improper buffer restrictions for some Intel(R) Xeon(R) Processor firmware with SGX enabled may allow a privileged user to potentially…
• CVE-2025-26403 — CVSS 7.2 (high): Out-of-bounds write in the memory subsystem for some Intel(R) Xeon(R) 6 processors when using Intel(R) SGX or Intel(R) TDX may allow a…
• CVE-2024-24853 — CVSS 7.2 (high): Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a…
• CVE-2025-20103 — CVSS 6.5 (medium): Insufficient resource pool in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially…
• CVE-2025-20054 — CVSS 6.5 (medium): Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially enable…
• CVE-2024-45332 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect…
• CVE-2024-43420 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel…
• CVE-2025-24495 — CVSS 5.6 (medium): Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow an authenticated…
• CVE-2024-28956 — CVSS 5.6 (medium): Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow…
• CVE-2025-20623 — CVSS 5.6 (medium): Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R)…
• CVE-2025-20012 — CVSS 4.9 (medium): Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated user to potentially enable information…
• CVE-2025-31648 — CVSS 3.9 (low): Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and…